Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design
نویسندگان
چکیده
Paper is devoted to a design FPGA problem regarding increase in trustworthiness of the results calculated in digital components of computer systems. The modern CAD solves this problem by implementation of significant hardware redundancy in fault tolerant decisions. The method for increase in trustworthiness of the results calculated on FPGA with the LUT-oriented architecture is offered. This method is directed to improving of the ready project without change of its hardware decision. The method generates 16 versions in programming of LUT memory and suggests selecting the best version by the given criterion. The method is shown on the example of masking of short circuit between LUT inputs. The method allows selecting the decision taking into account risk-value of bits in LUT memory.
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تاریخ انتشار 2016